1. First go to File and then New Project
2. Write Project Name and Description, if you want you can change location where your project will be saved. Click Next
3. In the New Project wizard, select appropriate options. If you are new like me then set the parameters as shown and click next.
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4. A project summary is displayed, click finish.
5. Screen as shown below is displayed, make sure View is selected to Implementation.
6. Now right click on not_gate and select New Source.
7. Select VHDL Module in New Source Wizard. Write File name and click next.
8. If you want you can Define ports in wizard, but in present project I will define it in code only. Click next.
9. A summary is displayed, click Finish.
10. Write your code in the editor window.
11. Now to create test bench, right click again at not gate and select New Source.
12. Select VHDL Test Bench from New Source Wizard, write file name and click Next.
13. Make sure your VHDL module is associated with test bench. Click Next.
14. A summary is displayed, click Finish.
15. Write Test Bench code and click Save.
16. Check syntax for both files i.e. VHDL Module and Test Bench.
17. Click on Simulation in the view.
18. Double click Behavioral Syntax check.
19. Double click Simulate Behavioral Model.
20. ISim will run simulation and result will be displayed.
21. To view schematic click back to Implementation in View and double click View RTL Schematic.
22. A window is opened, click Start with the Explorer Wizard and then click OK.
23. Add the desired signals you want to display in Schematic.
24. Schematic will be displayed.
24. Schematic will be displayed.
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